In modern data processing systems, information needs to be processed, stored and read with as little error as possible. As memory size increases, the likelihood of an error rises, which in the worst case can result in the system crashing.
Memory chips, such as DRAMs, SRAMs or ROMs, are therefore tested precisely before they are installed in a finished product, such as a PC.
The memory chips can be checked for faults at several times in the memory chips' manufacturing process. A first test on the chips is normally effected at wafer level (the chip is still in the raw state and has not yet been inserted into a package), with faulty memory cells being identified and repaired by laser cutter, for example.
If the memory chip is already in a package, a fault can be located and repaired using a tester, for example. To this end, the chip needs to have redundant memory cells which are activated by means of e-fuses (electrically activatable fuses), for example.
The checking routines applied during the tests can never fully check a memory chip with certainty, however, and therefore have gaps. During normal operation of a DIMM module (DIMM: Dual Inline Memory Module), data combinations can therefore arise which provoke a fault. In this case, the end user has no way of locating and repairing faults.
It is known practice for data processing units to incorporate an error identification algorithm (ECC algorithm; ECC: Error Correction Code) which can identify and correct single-bit errors and possibly also multibit errors. In this case, however, error correction is performed exclusively using correction algorithms and leaves the actual cause of the error, namely the hardware fault in the chip, untouched.